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ltc3728l-1 1 3728l1fc typical application features applications description dual, 550khz, 2-phase synchronous regulator the ltc ? 3728l-1 is a dual high performance step-down switching regulator controller that drives all n-channel synchronous power mosfet stages. a constant frequency current mode architecture allows phase-lockable frequency of up to 550khz. power loss and noise due to the esr of the input capacitors are minimized by operating the two controller output stages out of phase. the ltc3728l-1 is identical to the ltc3728l except that the ltc3728l-1 lacks the over current latchoff feature. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the precision 0.8v reference and power good output indicator are compatible with future microproces- sor generations, and a wide 4.5v to 28v (30v maximum/ 35v for ltc3728li-1) input supply range encompasses all battery chemistries. a run/ss pin for each controller provides soft-start. current foldback limits mosfet dissipation during short- circuit conditions. the fcb mode pin can select among burst mode operation, constant frequency mode and continuous inductor current mode or regulate a secondary winding. the ltc3728l-1 includes a power good output pin that indicates when both outputs are within 7.5% of their designed set point. figure 1. high ef? ciency dual 5v/3.3v step-down converter n dual, 180 phased controllers reduce required input capacitance and power supply induced noise n opti-loop ? compensation minimizes c out n 1.5% output voltage accuracy n power good output voltage indicator n phase-lockable fixed frequency 250khz to 550khz n over current latchoff disabled n wide v in range: 4.5v to 28v (35v for ltc3728li-1) operation n very low dropout operation: 99% duty cycle n adjustable soft-start current ramping n foldback output current limiting n output overvoltage protection n low shutdown i q : 20a n 5v and 3.3v standby regulators n 3 selectable operating modes: constant frequency, burst mode ? operation and pwm n 5mm 5mm qfn and 28-lead narrow ssop packages n notebook and palmtop computers n telecom systems n portable instruments n battery-operated digital devices n dc power distribution systems l , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5929620, 6177787, 6144199, 5471178, 5994885, 6100678. + 4.7f d3 d4 m1 c b1 , 0.1f r2 105k 1% 1000pf l1 3.2h c c1 220pf 1f ceramic c in 22f50v ceramic + c out1 47f6v sp r sense1 0.01 r120k 1% r c1 15k v out1 5v5a m2 c b2 , 0.1f r4 63.4k 1% l2 3.2h c c2 220pf 1000pf + c out 56f 6v sp r sense2 0.01 r3 20k 1% r c2 15k v out2 3.3v5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd sense1 + sense2 + sense1 C sense2 C v osense1 v osense2 i th1 i th2 v in pgood intv cc run/ss1 run/ss2 v in 5.2v to 28v m1, m2: fds6982s 3728l1 f01 c ss1 0.1f c ss2 0.1f ltc3728l-1 pllin f in 500khz downloaded from: http:///
ltc3728l-1 2 3728l1fc absolute maximum ratings input supply voltage (v in ) .........................30v to C 0.3v input supply voltage (v in ) ltc3728li-1 ....35v to C 0.3v top side driver voltages (boost1, boost2) ............................... 36v to C0.3v (boost1, boost2) ltc3728li-1 .......... 38v to C0.3v switch voltage (sw1, sw2) ........................... 30v to C5v switch voltage (sw1, sw2) ltc3728li-1 ... 35v to C0.3v intv cc, extv cc , run/ss1, run/ss2, (boost1-sw1), (boost2-sw2), pgood ......................... 7v to C0.3v intv cc, extv cc ltc3728li-1 ....................... 8v to C0.3v sense1 + , sense2 + , sense1 C , sense2 C voltages .....................(1.1)intv cc to C0.3v (note 1) 12 3 4 5 6 7 8 9 1011 12 13 14 top view gn package 28-lead narrow plastic ssop 2827 26 25 24 23 22 21 20 19 18 17 16 15 run/ss1 sense1 + sense C v osense1 pllfltr pllin fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 C sense2 + pgoodtg1 sw1 boost1 v in bg1extv cc intv cc pgndbg2 boost2 sw2 tg2 run/ss2 t jmax = 125c, ja = 95c/w 32 31 30 29 28 27 26 25 9 10 11 12 13 top view 33 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 v osense1 pllfltr pllin fcb i th1 sgnd 3.3v out i th2 boost1v in bg1extv cc intv cc pgndbg2 boost2 ncsense1 C sense1 + ncrun/ss1 pgood tg1 sw1 v osense2 nc sense2 C sense2 + run/ss2 tg2 sw2 nc uh package 32-lead (5mm s 5mm) plastic qfn t jmax = 125c, ja = 34c/w exposed pad (pin 33) is gnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking package description temperature range ltc3728legn-1#pbf ltc3728legn-1#trpbf ltc3728legn-1 28-lead narrow plastic ssop C40c to 85c ltc3728lign-1#pbf ltc3728lign-1#trpbf ltc3728lign-1 28-lead narrow plastic ssop C40c to 85c ltc3728leuh-1#pbf ltc3728leuh-1#trpbf 728le1 32-lead (5mm 5mm) plastic dfn C40c to 85c ltc3728liuh-1#pbf ltc3728liuh-1#trpbf 3728l1 32-lead (5mm 5mm) plastic dfn C40c to 85c lead based finish tape and reel part marking package description temperature range ltc3728legn-1 ltc3728legn-1#tr ltc3728legn-1 28-lead narrow plastic ssop C40c to 85c ltc3728lign-1 ltc3728lign-1#tr ltc3728lign-1 28-lead narrow plastic ssop C40c to 85c ltc3728leuh-1 ltc3728leuh-1#tr 728le1 32-lead (5mm 5mm) plastic dfn C40c to 85c ltc3728liuh-1 ltc3728liuh-1#tr 3728l1 32-lead (5mm 5mm) plastic dfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ pllin, pllfltr, fcb, voltage .............. intv cc to C0.3v i th1, i th2 , v osense1 , v osense2 voltages .... 2.7v to C0.3v peak output current <10s (tg1, tg2, bg1, bg2) .....3a intv cc peak output current ..................................40ma operating temperature range (note 7).... C40c to 85c junction temperature (note 2) ............................. 125c storage temperature range ................... C65c to 125c re? ow peak body temperature (uh package) ...... 260c lead temperature (soldering, 10 sec) gn package ...................................................... 300c downloaded from: http:///
ltc3728l-1 3 3728l1fc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 15v, v run/ss1, 2 = 5v unless otherwise noted. symbol parameter conditions min typ max units main control loopsv osense1, 2 regulated feedback voltage (note 3); i th1, 2 voltage = 1.2v 0.788 0.800 0.812 v i vosense1, 2 feedback current (note 3) C 5 C50 na v reflnreg reference voltage line regulation v in = 3.6v to 30v (note 3) 0.002 0.02 %/v v loadreg output voltage load regulation (note 3) measured in servo loop; i th voltage = 1.2v to 0.7v measured in servo loop; i th voltage = 1.2v to 2.0v 0.1 C 0.1 0.5 C0.5 %% g m1, 2 transconductance ampli? er g m i th1, 2 = 1.2v; sink/source 5a; (note 3) 1.3 mmho g mgbw1, 2 transconductance ampli? er gbw i th1, 2 = 1.2v; (note 3) 3 mhz i q input dc supply current normal mode shutdown (note 4)v in = 15v; extv cc tied to v out1 ; v out1 = 5v v run/ss1, 2 = 0v 450 20 35 aa v fcb forced continuous threshold 0.76 0.800 0.84 v i fcb forced continuous pin current v fcb = 0.85v C 0.50 C0.18 C0.1 a v binhibit burst inhibit (constant frequency) threshold measured at fcb pin 4.3 4.8 v uvlo undervoltage lockout v in ramping down 3.5 4 v v ovl feedback overvoltage lockout measured at v osense1, 2 0.84 0.86 0.88 v i sense sense pins total source current (each channel); v sense1 C , 2 C = v sense1 + , 2 + = 0v C90 C60 a df max maximum duty factor in dropout 98 99.4 % i run/ss1, 2 soft-start charge current v run/ss1, 2 = 1.9v 0.5 1.2 a v run/ss1, 2 on run/ss pin on threshold v run/ss1, v run/ss2 rising 1.0 1.5 2.0 v v sense(max) maximum current sense threshold v osense1, 2 = 0.7v,v sense1 C , 2 C = 5v v osense1, 2 = 0.7v,v sense1 C , 2 C = 5v 6562 7575 8588 mvmv tg1, 2 t r tg1, 2 t f tg transition time: rise time fall time (note 5)c load = 3300pf c load = 3300pf 5555 100100 nsns bg1, 2 t r bg1, 2 t f bg transition time: rise time fall time (note 5)c load = 3300pf c load = 3300pf 4545 100 90 nsns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 80 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver 80 ns t on(min) minimum on-time tested with a square wave (note 6) 100 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v 4.8 5.0 5.2 v v ldo int intv cc load regulation i cc = 0 to 20ma, v extvcc = 4v 0.2 2.0 % v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 100 200 mv v extvcc extv cc switchover voltage i cc = 20ma, extv cc ramping positive 4.5 4.7 v v ldohys extv cc hysteresis 0.2 v oscillator and phase-locked loopf nom nominal frequency v pllfltr = 1.2v 360 400 440 khz f low lowest frequency v pllfltr = 0v 230 260 290 khz f high highest frequency v pllfltr 2.4v 480 550 590 khz r pllin pllin input resistance 50 k downloaded from: http:///
ltc3728l-1 4 3728l1fc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 15v, v run/ss1, 2 = 5v unless otherwise noted. symbol parameter conditions min typ max units i pllfltr phase detector output current sinking capability sourcing capability f pllin < f osc f pllin > f osc C15 15 aa 3.3v linear regulatorv 3.3out 3.3v regulator output voltage no load 3.2 3.35 3.45 v v 3.3il 3.3v regulator load regulation i 3.3 = 0 to 10ma 0.5 2 % v 3.3vl 3.3v regulator line regulation 6v < v in < 30v 0.05 0.2 % i 3.3leak leakage current in shutdown v run/ss1 = 0v; v run/ss2 = 0v, v in = 3v 10 50 a pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level, either controller v osense with respect to set output voltage v osense ramping negative v osense ramping positive C6 6 C7.5 7.5 C 9.5 9.5 %% ef? ciency vs output current and mode (figure 13) ef? ciency vs output current (figure 13) ef? ciency vs input voltage (figure 13) typical performancce characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc3728luh-1: t j = t a + (p d ? 34c/w) ltc3728lgn-1: t j = t a + (p d ? 95c/w) note 3: the ic is tested in a feedback loop that servos v ith1, 2 to a speci? ed voltage and measures the resultant v osense1, 2. note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 5: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels.note 6: the minimum on-time condition is speci? ed for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section).note 7: the ltc3728le-1 are guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3728li-1 is guaranteed to meet performance speci? cations over the full C40c to 85c operating temperature range output current (a) 0.001 0 efficiency (%) 10 30 40 50 100 70 0.01 0.1 1 3728l1 g01 20 80 90 60 10 forcedcontinuous mode (pwm) constant frequency (burst disable) burst mode operation v in = 15v v out = 5v f = 250khz output current (a) 0.001 efficiency (%) 70 80 10 3728l1 g02 6050 0.01 0.1 1 100 90 v in = 10v v in = 15v v in = 7v v in = 20v v out = 5v f = 250khz input voltage (v) 5 efficiency (%) 70 80 3728l1 g03 60 50 15 25 35 100 v out = 5v i out = 3a f = 250khz 90 downloaded from: http:///
ltc3728l-1 5 3728l1fc typical performance characteristics supply current vs input voltage and mode (figure 13) extv cc voltage drop intv cc and extv cc switch voltage vs temperature internal 5v ldo line regulation maximum current sense threshold vs duty factor maximum current sense threshold vs percent of nominal output voltage (foldback) maximum current sense threshold vs v run/ss (soft-start) maximum current sense threshold vs sense common mode voltage current sense threshold vs i th voltage input voltage (v) 05 0 supply current (a) 400 1000 10 20 25 3728l1 g04 200 800 600 15 30 shutdown bothcontrollers on current (ma) 0 extv cc voltage drop (mv) 150 200 40 3728l1 g05 100 50 0 10 20 30 temperature (c) C50 intv cc and extv cc switch voltage (v) 4.95 5.00 5.05 25 75 3728l1 g06 4.90 4.85 C25 0 50 100 125 4.80 4.70 4.75 intv cc voltage extv cc switchover threshold input voltage (v) 0 4.8 4.9 5.1 15 25 3728l1 g07 4.74.6 51 0 20 30 4.54.4 5.0 intv cc voltage (v) i load = 1ma duty factor (%) 0 0 v sense (mv) 25 50 75 20 40 60 80 3728l1 g08 100 percent on nominal output voltage (%) 0 v sense (mv) 40 50 60 100 3728l1 g09 3020 0 25 50 75 10 8070 v run/ss (v) 0 0 v sense (mv) 20 40 60 80 1234 3728l1 g10 56 v sense(cm) = 1.6v common mode voltage (v) 0 v sense (mv) 72 76 80 4 3728l1 g11 68 64 60 1 2 3 5 v ith (v) 0 v sense (mv) 30 50 70 90 2 3728l1 g12 10 C10 20 40 60 80 0 C20 C30 0.5 1 1.5 2.5 downloaded from: http:///
ltc3728l-1 6 3728l1fc typical performance characteristics load regulation v ith vs v run/ss sense pins total source current maximum current sense threshold vs temperature dropout voltage vs output current (figure 14) run/ss current vs temperature soft-start up (figure 13) load step (figure 13) load step (figure 13) load current (a) 0 normalized v out (%) C0.2 C0.1 4 3728l1 g13 C0.3C0.4 1 2 3 5 0.0 fcb = 0vv in = 15v figure 13 v run/ss (v) 0 0 v ith (v) 0.5 1.0 1.5 2.0 2.5 1 234 3728l1 g14 56 v osense = 0.7v v sense common mode voltage (v) 0 i sense (a) 0 3728l1 g15 C50 C100 24 50 100 6 temperature (c) C50 C25 70 v sense (mv) 74 80 0 50 75 3728l1 g17 72 78 76 25 100 125 output current (a) 0 0 dropout voltage (v) 1 2 3 4 0.5 1.0 1.5 2.0 3728l1 g18 2.5 3.0 3.5 4.0 r sense = 0.015 r sense = 0.010 v out = 5v temperature (c) C50 C25 0 run/ss current (a) 0.2 0.6 0.8 1.0 75 100 50 1.8 3728l1 g25 0.4 0 25 125 1.2 1.4 1.6 3728l1 g19 v out 5v/div v run/ss 5v/div i l 2a/div 5ms/div v in = 15v v out = 5v 3728l1 g20 v out 200mv/div i l 2a/div 20s/div v in = 15v v out = 5v v pllfltr = 50v load step = 0a to 3a burst mode operation 3728l1 g21 v out 200mv/div i l 2a/div 20s/div v in = 15v v out = 5v v pllfltr = 50v load step = 0a to 3acontinuous mode downloaded from: http:///
ltc3728l-1 7 3728l1fc typical performance characteristics input source/capacitor instantaneous current (figure 13) burst mode operation (figure 13) constant frequency (burst inhibit) operation (figure 13) current sense pin input current vs temperature extv cc switch resistance vs temperature oscillator frequency vs temperature undervoltage lockout vs temperature 3728l1 g22 v in 200mv/div v sw1 10v/div v sw2 10v/div i in 2a/div 1s/div v in = 15v v out1 = 5v, v out2 = 3.3v v pllfltr = 0v i out5 = i out3.3 = 2a 3728l1 g23 v out 20mv/div i l 0.5a/div 10s/div v in = 15v v out = 5v v pllfltr = 0v v fcb = 5v i out = 20ma 3728l1 g24 v out 20mv/div i l 0.5a/div 2s/div v in = 15v v out = 5v v pllfltr = 0v v fcb = 5v i out = 20ma temperature (c) C50 C25 25 current sense input current (a) 29 35 0 50 75 3728l1 g26 27 33 31 25 100 125 v out = 5v temperature (c) C50 C25 0 extv cc switch resistance () 4 10 0 50 75 3728l1 g27 2 8 6 25 100 125 temperature (c) C50 400 500 700 25 75 3728l1 g28 300200 C25 0 50 100 125 100 0 600 frequency (khz) v pllfltr = 2.4v v pllfltr = 1.2v v pllfltr = 0v temperature (c) C50 undervoltage lockout (v) 3.40 3.45 3.50 25 75 3728l1 g29 3.35 3.30 C25 0 50 100 125 3.25 3.20 downloaded from: http:///
ltc3728l-1 8 3728l1fc pin functions v osense1 , v osense2 : error ampli? er feedback input. receives the remotely-sensed feedback voltage for each controller from an external resistive divider across the output. pllfltr: filter connection for phase-locked loop. alter- natively, this pin can be driven with an ac or dc voltage source to vary the frequency of the internal oscillator. pllin: external synchronization input to phase detector. this pin is internally terminated to sgnd with 50k. the phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the pllin signal. fcb: forced continuous control input. this input acts on both controllers and is normally used to regulate a secondary winding. pulling this pin below 0.8v will force continuous synchronous operation. i th1, i th2 : error ampli? er output and switching regulator compensation point. each associated channels current comparator trip point increases with this control voltage. sgnd: small signal ground. common to both controllers, this pin must be routed separately from high current grounds to the common (C) terminals of the c out capacitors. 3.3v out : linear regulator output. capable of supplying 10ma dc with peak currents as high as 50ma.nc: no connect. sense2 C , sense1 C : the (C) input to the differential cur- rent comparators.sense2 + , sense1 + : the (+) input to the differential current comparators. the i th pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold. run/ss2, run/ss1: combination of soft-start and run control inputs. a capacitor to ground at each of these pins sets the ramp time to full output current. forcing either of these pins back below 1.0v causes the ic to shut down the circuitry required for that particular controller. tg2, tg1: high current gate drives for top n-channel mosfets. these are the outputs of ? oating drivers with a voltage swing equal to intv cc C 0.5v superimposed on the switch node voltage sw. sw2, sw1: switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . boost2, boost1: bootstrapped supplies to the top side floating drivers. capacitors are connected between the boost and switch pins and schottky diodes are tied between the boost and intv cc pins. voltage swing at the boost pins is from intv cc to (v in + intv cc ). bg2, bg1: high current gate drives for bottom (synchro- nous) n-channel mosfets. voltage swing at these pins is from ground to intv cc . pgnd: driver power ground. connects to the sources of bottom (synchronous) n-channel mosfets, anodes of the schottky recti? ers and the (C) terminal(s) of c in . intv cc : output of the internal 5v linear low dropout regulator and the extv cc switch. the driver and control circuits are powered from this voltage source. must be decoupled to power ground with a minimum of 4.7f tantalum or other low esr capacitor. extv cc : external power input to an internal switch con- nected to intv cc . this switch closes and supplies v cc power, bypassing the internal low dropout regulator, when- ever extv cc is higher than 4.7v. see extv cc connection in applications section. do not exceed 7v on this pin.v in : main supply pin. a bypass capacitor should be tied between this pin and the signal ground pin.pgood: open-drain logic output. pgood is pulled to ground when the voltage on either v osense pin is not within 7.5% of its set point.exposed pad (uh package only) : signal ground. must be soldered to the pcb, providing a local ground for the control components of the ic, and be tied to the pgnd pin under the ic. downloaded from: http:///
ltc3728l-1 9 3728l1fc functional diagram switch logic C + 0.8v 4.8v 5v v in v in 4.5v binh clk2 clk1 0.18a r6r5 + C fcb + C C + C + C + v ref internal supply 3.3v out intv cc r lp c lp 3v fcb intv cc sgnd (uh package pad) + 5v ldoreg sw shdn 0.55v top boost tg c b c in d 1 d b pgnd bot bg intv cc intv cc v in + c out v out 3728l1 f02 r sense r2 + v osense drop out det run soft start bot top on sr qq oscillator phase det pllfltr pllin fcb ea 0.86v 0.80v ov v fb 1.2a 6v r1 C + r c 4(v fb ) rst shdn run/ss i th c c c c2 c ss 4(v fb ) 0.86v slope comp 3mv + C C + sense C sense + intv cc 30k 45k 2.4v 45k 30k i1 i2 b duplicate for secondcontroller channel + C C + 50k f in + C + C + C + C pgood v osense1 v osense2 0.86v0.74v 0.86v 0.74v extv cc figure 2 downloaded from: http:///
ltc3728l-1 10 3728l1fc operation main control loop the ltc3728l-1 is a constant frequency, current mode step-down controller with two channels operating 180 degrees out of phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current com- parator, i 1 , resets the rs latch. the peak inductor current at which i 1 resets the rs latch is controlled by the voltage on the i th pin, which is the output of each error ampli? er ea. the v osense pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current increases, it causes a slight decrease in v osense relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current comparator i 2 , or the beginning of the next cycle.the top mosfet drivers are biased from ? oating bootstrap capacitor c b , which normally is recharged during each off cycle through an external diode when the top mosfet turns off. as v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about 400ns every tenth cycle to allow c b to recharge. the main control loop is shut down by pulling the run/ss pin low. releasing run/ss allows an internal 1.2a cur- rent source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, the i th pin voltage is gradually released allowing normal, full-current operation. when both run/ss1 and run/ss2 are low, all controller functions are shut down, including the 5v regulator. low current operation the fcb pin is a multifunction pin providing two func- tions: 1) to provide regulation for a secondary winding by temporarily forcing continuous pwm operation on both controllers; and 2) to select between two modes of low current operation. when the fcb pin voltage is below 0.8v, the controller forces continuous pwm cur- rent mode operation. in this mode, the top and bottom mosfets are alternately turned on to maintain the output voltage independent of direction of inductor current. when the fcb pin is below v intvcc C 2v but greater than 0.8v, the controller enters burst mode operation. burst mode operation sets a minimum output current level before inhibiting the top switch and turns off the synchronous mosfet(s) when the inductor current goes negative. this combination of requirements will, at low currents, force the i th pin below a voltage threshold that will temporarily inhibit turn-on of both output mosfets until the output voltage drops. there is 60mv of hyster- esis in the burst comparator b tied to the i th pin. this hysteresis produces output signals to the mosfets that turn them on for several cycles, followed by a variable sleep interval depending upon the load current. the resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error ampli? er gain block. frequency synchronizationthe phase-locked loop allows the internal oscillator to be synchronized to an external source via the pllin pin. the output of the phase detector at the pllfltr pin is also the dc frequency control input of the oscillator that operates over a 260khz to 550khz range corresponding to a dc voltage input from 0v to 2.4v. when locked, the pll aligns the turn on of the top mosfet to the rising edge of the synchronizing signal. when pllin is left open, the pllfltr pin goes low, forcing the oscillator to minimum frequency. constant frequency operation when the fcb pin is tied to intv cc , burst mode opera- tion is disabled and the forced minimum output current requirement is removed. this provides constant frequency, discontinuous current (preventing reverse inductor cur- rent) operation over the widest possible output current range. this constant frequency operation is not as ef? cient (refer to functional diagram) downloaded from: http:///
ltc3728l-1 11 3728l1fc operation (refer to functional diagram) as burst mode operation, but does provide a lower noise, constant frequency operating mode down to approximately 1% of the designed maximum output current. continuous current (pwm) operation tying the fcb pin to ground will force continuous current operation. this is the least ef? cient operating mode, but may be desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, the controller will cause current to ? ow back into the input ? lter capacitor. if large enough, this element will prevent the input sup-ply from boosting to unacceptably high levels; see c out selection in the applications information section. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open, an internal 5v low dropout linear regulator supplies intv cc power. if extv cc is taken above 4.7v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc to intv cc . this al- lows the intv cc power to be derived from a high ef? ciency external source such as the output of the regulator itself or a secondary winding, as described in the applications information section. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>7.5%) as well as other more serious condi- tions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good (pgood) pin the pgood pin is connected to an open drain of an internal mosfet. the mosfet turns on and pulls the pin low when either output is not within 7.5% of the nominal output level as determined by the resistive feedback divider. when both outputs meet the 7.5% requirement, the mosfet is turned off within 10s and the pin is allowed to be pulled up by an external resistor to a source of up to 7v. foldback current the run/ss capacitors are used initially to limit the inrush current of each switching regulator. foldback current limit- ing is activated when the output voltage falls below 70% of its nominal level. if a short is present, a safe, low output current is provided due to the internal current foldback and actual power wasted is low due to the ef? cient nature of the current mode switching regulator. theory and benefits of 2-phase operation the ltc1628 and the ltc3728l-1 family of dual high ef- ? ciency dc/dc controllers brings the considerable bene? ts of 2-phase operation to portable applications for the ? rst time. notebook computers, pdas, handheld terminals and automotive electronics will all bene? t from the lower input ? ltering requirement, reduced electromagnetic interference (emi) and increased ef? ciency associated with 2-phase operation.why the need for 2-phase operation? up until the 2-phase family, constant-frequency dual switching regulators operated both channels in phase (i.e., single-phase operation). this means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. these large amplitude current pulses increased the total rms current ? owing from the input capacitor, requiring the use of more expensive input capacitors and increasing both emi and losses in the input capacitor and battery. with 2-phase operation, the two channels of the dual- switching regulator are operated 180 degrees out of phase. this effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. the result is a signi? cant reduction in total rms input current, which in turn allows less expen sive input capacitors to be used, reduces shielding requirements for emi and improves real world operating ef? ciency. downloaded from: http:///
ltc3728l-1 12 3728l1fc operation (refer to functional diagram) figure 3 compares the input waveforms for a representa- tive single-phase dual switching regulator to the ltc1628 2-phase dual switching regulator. an actual measurement of the rms input current under these conditions shows that 2- phase operation dropped the input current from 2.53a rms to 1.55a rms . while this is an impressive reduction in itself, remember that the power losses are proportional to i rms 2 , meaning that the actual power wasted is reduced by a fac-tor of 2.66. the reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. of course, the improvement afforded by 2-phase opera- tion is a function of the dual switching regulators relative duty cycles which, in turn, are dependent upon the input voltage v in (duty cycle = v out /v in ). figure 4 shows how the rms input current varies for single-phase and 2-phase operation for 3.3v and 5v regulators over a wide input voltage range. it can readily be seen that the advantages of 2-phase opera- tion are not just limited to a narrow operating range, but in fact extend over a wide region. a good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. figure 3. input waveforms comparing single-phase (a) and 2-phase (b) operation for dual switching regulators converting 12v to 5v and 3.3v at 3a each. the reduced input ripple with the ltc1628 2-phase regulator allows less expensive input capacitors, reduces shielding requirements for emi and improves ef? ciency 3728l1 f03a 5v switch 20v/div 3.3v switch 20v/div input current 5a/div input voltage 500mv/div i in(meas) = 2.53a rms 3728l1 f03b i in(meas) = 1.55a rms (a) (b) figure 4. rms input current comparison input voltage (v) 0 input rms current (a) 3.02.5 2.0 1.5 1.0 0.5 0 10 20 30 40 3728l1 f04 single phasedual controller 2-phase dual controller v o1 = 5v/3a v o2 = 3.3v/3a downloaded from: http:///
ltc3728l-1 13 3728l1fc figure 1 on the ? rst page is a basic ltc3728l-1 applica- tion circuit. external component selection is driven by the load requirement, and begins with the selection of r sense and the inductor value. next, the power mosfets and d1 are selected. finally, c in and c out are selected. the circuit shown in figure 1 can be con? gured for operation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense is chosen based on the required output current. the current comparator has a maximum threshold of 75mv/r sense and an input common mode range of sgnd to 1.1(intv cc ). the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, i l . allowing a margin for variations in the ic and external component values yields: r sense = 50mv i ma x when using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criteria for buck regulators operating at greater than 50% duty factor. a curve is provided to estimate this reduction in peak output current level depending upon the operating duty factor. operating frequency the ic uses a constant frequency phase-lockable ar- chitecture with the frequency determined by an internal capacitor. this capacitor is charged by a ? xed current plus an additional current which is proportional to the voltage applied to the pllfltr pin. refer to phase-locked loop and frequency synchronization in the applications infor- mation section for additional information. a graph for the voltage applied to the pllfltr pin vs frequency is given in figure 5. as the operating frequency is increased the gate charge losses will be higher, reducing applications information figure 5. pllfltr pin voltage vs frequency ef? ciency (see ef? ciency considerations). the maximum switching frequency is approximately 550khz. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is ef? ciency. a higher frequency generally results in lower ef? ciency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance or frequency and increases with higher v in : i l = 1 (f)(l ) v out 1? v out v i n accepting larger values of i l allows the use of low in- ductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is i l =0.3(i max ). the maximum i l occurs at the maximum input voltage. the inductor value also has secondary effects. the tran- sition to burst mode operation begins when the average inductor current required results in a peak current below operating frequency (khz) 200 300 400 500 600 pllfltr pin voltage (v) 3728l1 f05 2.52.0 1.5 1.0 0.5 0 downloaded from: http:///
ltc3728l-1 14 3728l1fc applications information 25% of the current limit determined by r sense . lower inductor values (higher i l ) will cause this to occur at lower load currents, which can cause a dip in ef? ciency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection usually, high inductance is preferred for small current ripple and low core loss. unfortunately, increased induc- tance requires more turns of wire or a smaller air gap in the inductor core, resulting in high copper loss or low saturation current. once the value of l is known, the actual inductor must be selected. there are two popular types of core material of commercial available inductors. ferrite core inductors usually have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura- tion. however, ferrite core saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. one advantage of the ltc3728l-1 is its current mode control that detects and limits cycle-by-cycle peak inductor current. therefore, accurate and fast protection is achieved if the inductor is saturated in steady state or during transient mode. powdered iron core inductors usually saturate soft, which means the inductance drops in a linear fashion when the current increases. however, the core loss of the powder iron inductor is usually higher than the ferrite inductor. so designs with high switching frequency should also address inductor core loss. inductor manufacturers usually provide inductance, dcr, (peak) saturation current and (dc) heating current ratings in the inductor data sheet. a good supply design should not exceed the saturation and heating current rating of the inductor. power mosfet and d1 selection two external power mosfets must be selected for each controller in the ltc3728l-1: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss speci? cation for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately ? at divided by the speci? ed change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve speci? ed v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v i n synchronous switch duty cycle = v in ?v out v i n the mosfet power dissipations at maximum output current are given by: p main = v out v i n i max () 2 1 + () r ds(on) + v in () 2 i max 2
r dr () c miller () ? 1 v intvcc ?v thmi n + 1 v thmi n f () p sync = v in ?v out v i n i max () 2 1 + () r ds(on) downloaded from: http:///
ltc3728l-1 15 3728l1fc applications information where is the temperature dependency of r ds(on) and r dr (approximately 4) is the effective driver resistance at the mosfets miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current ef? ciency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher ef? ciency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. the schottky diode d1 shown in figure 1 conducts dur- ing the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in ef? ciency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small aver- age current. larger diodes result in additional transition losses due to their larger junction capacitance. schottky diodes should be placed in parallel with the synchronous mosfets when operating in pulse-skip mode or in burst mode operation. c in and c out selection the selection of c in is simpli? ed by the multiphase ar- chitecture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst case rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms current requirement. increasing the output current, drawn from the other out-of-phase controller, will actually decrease the input rms ripple current from this maximum value (see figure 4). the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. the type of input capacitor, value and esr rating have ef? ciency effects that need to be considered in the selec- tion process. the capacitance value chosen should be suf? cient to store adequate charge to keep high peak battery currents down. 20f to 40f is usually suf? cient for a 25w output supply operating at 200khz. the esr of the capacitor is important for capacitor power dissipation as well as overall battery ef? ciency. all of the power (rms ripple current ? esr) not only heats up the capacitor but wastes power from the battery. medium voltage (20v to 35v) ceramic, tantalum, os-con and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramics have very high voltage coef? cients and may have audible piezoelectric effects; tantalums need to be surge-rated; os-cons suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics higher esr and dryout possibility require several to be used. multiphase systems allow the lowest amount of capacitance overall. as little as one 22f or two to three 10f ceramic capacitors are an ideal choice in a 20w to 35w power supply due to their extremely low esr. even though the capacitance at 20v is substantially below their rating at zero-bias, very low esr loss makes ceramics an ideal candidate for highest ef? ciency battery operated systems. also consider parallel ceramic and high quality electrolytic capacitors as an effective means of achieving esr and bulk capacitance goals. in continuous mode, the source current of the top n-channel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v out v in v out () 1/ 2 v i n downloaded from: http:///
ltc3728l-1 16 3728l1fc applications information this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. the bene? t of the ltc3728l-1 multiphase clocking can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the interleaving of current pulses through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. remember that input protection fuse resistance, battery resistance and pc board trace resistance losses are also reduced due to the reduced peak currents in a multi- phase system. the overall bene? t of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the ef? ciency test- ing. the drains of the two top mosfets should be placed within 1cm of each other and share a common c in (s). separating the drains and c in may produce undesirable voltage and current resonances at v in . the selection of c out is driven by the required effective series resistance (esr). typically once the esr require- ment is satis? ed the capacitance is adequate for ? ltering. the output ripple (v out ) is determined by: v out i l esr + 1 8fc ou t where f = operating frequency, c out = output capacitance, and i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. with i l = 0.3i out(max) the output ripple will typically be less than 50mv at the maximum v in assuming: c out recommended esr < 2 r sense and c out > 1/(8fr sense ) the ? rst condition relates to the ripple current into the esr of the output capacitance while the second term guarantees that the output capacitance does not signi? cantly discharge during the operating frequency period due to ripple current. the choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage at or below 50mv. the i th pin opti-loop compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. manufacturers such as nichicon, nippon chemi-con and sanyo can be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest (esr)(size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recommended to reduce the inductance effects. in surface mount applications multiple capacitors may need to be used in parallel to meet esr, rms cur- rent handling and load step requirements. aluminum electrolytic, dry tantalum and special polymer capaci- tors are available in surface mount packages. special polymer surface mount capacitors offer very low esr but have lower storage capacity per unit volume than other capacitor types. these capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. tantalum capacitors offer the highest capacitance density and are often used as output capaci- tors for switching regulators having controlled soft-start. several excellent surge-tested choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors can be used downloaded from: http:///
ltc3728l-1 17 3728l1fc applications information in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long term reliability. a typical application will require several to many aluminum electrolytic capacitors in parallel. a combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. other capacitor types include nichicon pl series, panasonic sp, nec neocap, cornell dubilier esre and sprague 595d series. consult manufacturers for other speci? c recommendations. intv cc regulator an internal p-channel low dropout regulator produces 5v at the intv cc pin from the v in supply pin. intv cc powers the drivers and internal circuitry within the ic. the intv cc pin regulator can supply a peak current of 50ma and must be bypassed to ground with a minimum of 4.7f tantalum, 10f special polymer, or low esr type electrolytic capacitor. a 1f ceramic capacitor placed di- rectly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between channels. higher input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ic to be exceeded. the system supply current is normally dominated by the gate charge current. additional external loading of the intv cc and 3.3v linear regulators also needs to be taken into account for the power dissipation calculations. the total intv cc current can be supplied by either the 5v in- ternal linear regulator or by the extv cc input pin. when the voltage applied to the extv cc pin is less than 4.7v, all of the intv cc current is supplied by the internal 5v linear regulator. power dissipation for the ic in this case is high- est: (v in )(i intvcc ), and overall ef? ciency is lowered. the gate charge current is dependent on operating frequency as discussed in the ef? ciency considerations section. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the ic v in current is thermally limited to less than 67ma from a 24v supply when not using the extv cc pin as follows: t j = 70c + (67ma)(24v)(34c/w) = 125c use of the extv cc input pin reduces the junction tem- perature to: t j = 70c + (67ma)(5v)(34c/w) = 81c the absolute maximum rating for the intv cc pin is 40ma. dissipation should be calculated to also include any added current drawn from the internal 3.3v linear regulator. to prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum v in . extv cc connection the ic contains an internal p-channel mosfet switch connected between the extv cc and intv cc pins. when the voltage applied to extv cc rises above 4.7v, the internal regulator is turned off and the switch closes, connecting the extv cc pin to the intv cc pin thereby supplying internal power. the switch remains closed as long as the voltage applied to extv cc remains above 4.5v. this allows the mosfet driver and control power to be derived from the output during normal operation (4.7v < v out < 7v) and from the internal regulator when the output is out of regu- lation (start-up, short-circuit). if more current is required through the extv cc switch than is speci? ed, an external schottky diode can be added between the extv cc and intv cc pins. do not apply greater than 7v to the extv cc pin and ensure that extv cc < v in . signi? cant ef? ciency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(ef? ciency). for 5v regulators this supply means connecting the extv cc pin directly to v out . however, for 3.3v and other lower voltage regulators, additional circuitry is required to derive intv cc power from the output.the following list summarizes the four possible connec- tions for extv cc: 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting in an ef? ciency penalty of up to 10% at high input voltages. downloaded from: http:///
ltc3728l-1 18 3728l1fc applications information 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest ef? ciency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 7v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 4. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, ef? ciency gains can still be realized by connecting extv cc to an output- derived voltage that has been boosted to greater than 4.7v. this can be done with either the inductive boost winding as shown in figure 6a or the capacitive charge pump shown in figure 6b. the charge pump has the advantage of simple magnetics. topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged through external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the ? nal arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the ef? ciency has improved. if there is no change in input current, then there is no change in ef? ciency. output voltage the output voltages are each set by an external feedback resistive divider carefully placed across the output capacitor. the resultant feedback signal is compared with the internal precision 0.800v voltage reference by the error ampli? er. the output voltage is given by the equation: v out = 0.8v 1 + r2 r 1 where r1 and r2 are de? ned in figure 2. sense + /sense C pins the common mode input range of the current comparator sense pins is from 0v to (1.1)intv cc . continuous linear operation is guaranteed throughout this range allowing output voltage setting from 0.8v to 7.7v, depending upon the voltage applied to extv cc . a differential npn input figure 6a. secondary output loop & extv cc connection figure 6b. capacitive charge pump for extv cc extv cc fcbsgnd v in tg1 sw bg1 pgnd ltc3728l-1 r sense v out v sec + c out + 1f 3728l1 f06a n-ch n-ch r6 + c in v in t1 1:n optional extv cc connection5v < v sec < 7v r5 bat 85 extv cc v in tg1 sw bg1 pgnd ltc3728l-1 r sense v out vn2222ll + c out 3728l1 f06b n-ch n-ch + c in + 1f v in l1 bat85 bat85 bat85 0.22f downloaded from: http:///
ltc3728l-1 19 3728l1fc applications information stage is biased with internal resistors from an internal 2.4v source as shown in the functional diagram. this requires that current either be sourced or sunk from the sense pins depending on the output voltage. if the output voltage is below 2.4v current will ? ow out of both sense pins to the main output. the output can be easily preloaded by the v out resistive divider to compensate for the current comparators negative input bias current. the maximum current ? owing out of each pair of sense pins is: i sense + + i sense C = (2.4v C v out )/24k since v osense is servoed to the 0.8v reference voltage, we can choose r1 in figure 2 to have a maximum value to absorb this current. r1 (max) = 24k 0.8v 2.4v ? v ou t for v out < 2.4v regulating an output voltage of 1.8v, the maximum value of r1 should be 32k. note that for an output voltage above 2.4v, r1 has no maximum value necessary to absorb the sense currents; however, r1 is still bounded by the v osense feedback current.soft-start/run function the run/ss1 and run/ss2 pins are multipurpose pins that provide a soft-start function and a means to shut down the ltc3728l-1. soft-start reduces the input power sources surge currents by gradually increasing the controllers current limit (proportional to v ith ). this pin can also be used for power supply sequencing. an internal 1.2a current source charges up the c ss capaci- tor . when the voltage on run/ss1 (run/ss2) reaches 1.5v, the particular controller is permitted to start operating. as the voltage on run/ss increases from 1.5v to 3.0v, the internal current limit is increased from 25mv/r sense to 75mv/r sense . the output current limit ramps up slowly, taking an additional 1.25s/f to reach full current. the output current thus ramps up slowly, reducing the start- ing surge current required from the input power supply. if run/ss has been pulled all the way to ground there is a delay before starting of approximately: t delay = 1.5v 1.2 a c ss = 1.25s / f () c ss t iramp = 3v 1.5v 1.2 a c ss = 1.25s / f () c ss by pulling both run/ss pins below 1v, the ic is put into low current shutdown (i q = 20a). the run/ss pins can be driven directly from logic as shown in figure 7. diode d1 in figure 7 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. each run/ss pin has an internal 6v zener clamp (see functional diagram). because the ltc3728l-1 is designed for applications not requiring over current latchoff, no pull-up resistor is required on the run/ss pin to defeat latchoff. refer to the ltc3728l/ltc3728lx datasheet if this feature is required. fault conditions: current limit and current foldback the current comparators have a maximum sense volt- age of 75mv resulting in a maximum mosfet current of 75mv/r sense . the maximum value of current limit generally occurs with the largest v in at the highest ambi- figure 7. run/ss pin interfacing 3.3v or 5v run/ss d1 (a) (b) c ss run/ss c ss 3728l1 f07 downloaded from: http:///
ltc3728l-1 20 3728l1fc applications information ent temperature, conditions that cause the highest power dissipation in the top mosfet. each controller includes current foldback to help further limit load current when the output is shorted to ground. the foldback circuit is active even when the overload shutdown latch described above is overridden. if the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 75mv to 17mv. under short-circuit conditions with very low duty cycles, the controller will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time t on(min) of each controller (typically 100ns), the input voltage and inductor value: i l(sc) = t on(min) (v in /l) the resulting short-circuit current is: i sc = 25mv r sens e ? 1 2 i l(sc) fault conditions: overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. the crowbar causes huge currents to ? ow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the controller is operating. a comparator monitors the output for overvoltage con- ditions. the comparator (ov) detects overvoltage faults greater than 7.5% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the output of this comparator is only latched by the overvoltage condition itself and will therefore allow a switching regulator system having a poor pc layout to function while the design is being debugged. the bottom mosfet remains on continuously for as long as the ov condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. phase-locked loop and frequency synchronization the ic has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. this al- lows the top mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 50% around the center frequency f o . a voltage of 1.2v applied to the pllfltr pin corresponds to a frequency of approximately 400khz. the nominal operating frequency range of the ic is 260khz to 550khz. the phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the ex- ternal and internal oscillators. this type of phase detector will not lock up on input frequencies close to the harmonics of the vco center frequency. the pll hold-in range, f h , is equal to the capture range, f c: f h = f c = 0.5 f o (260khz-550khz) the output of the phase detector is a complementary pair of current sources charging or discharging the external ? lter network on the pllfltr pin. if the external frequency (f pllin ) is greater than the os- cillator frequency f 0sc , current is sourced continuously, downloaded from: http:///
ltc3728l-1 21 3728l1fc applications information pulling up the pllfltr pin. when the external frequency is less than f 0sc , current is sunk continuously, pulling down the pllfltr pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. thus the voltage on the pllfltr pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operat- ing point the phase comparator output is open and the ? lter capacitor c lp holds the voltage. the ics pllin pin must be driven from a low impedance source such as a logic gate located close to the pin. when using multiple ics for a phase-locked system, the pllfltr pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the masters frequency. a dc voltage of 0.7v to 1.7v applied to the master oscillators pllfltr pin is recommended in order to meet this requirement. the resultant operating frequency can range from 300khz to 500khz. the loop ? lter components (c lp , r lp ) smooth out the cur- rent pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the ? lter compo- nents c lp and r lp determine how fast the loop acquires lock. typically r lp =10k and c lp is 0.01f to 0.1f. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that each controller is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t on(min) < v out v in (f ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for each controller is approximately 100ns. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 150ns. this is of particular concern in forced continuous applica- tions with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a signi? cant amount of cycle skipping can occur with cor- respondingly larger current and voltage ripple. fcb pin operation the fcb pin can be used to regulate a secondary winding or as a logic level input. continuous operation is forced on both controllers when the fcb pin drops below 0.8v. during continuous mode, current ? ows continuously in the transformer primary. the secondary winding(s) draw current only when the bottom, synchronous switch is on. when primary load currents are low and/or the v in /v out ratio is low, the synchronous switch may not be on for a suf? cient amount of time to transfer power from the output capacitor to the secondary load. forced continuous opera- tion will support secondary windings providing there is suf? cient synchronous switch duty factor. thus, the fcb input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. with the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. the secondary output voltage v sec is normally set as shown in figure 6a by the turns ratio n of the transformer: v sec ? (n + 1) v out however, if the controller goes into burst mode operation and halts switching due to a light primary load current, then v sec will droop. an external resistive divider from v sec to the fcb pin sets a minimum voltage v sec(min) : v sec(min) 0.8v 1 + r6 r 5 where r5 and r6 are shown in figure 2. downloaded from: http:///
ltc3728l-1 22 3728l1fc applications information if v sec drops below this level, the fcb voltage forces temporary continuous switching operation until v sec is again above its minimum.in order to prevent erratic operation if no external connec- tions are made to the fcb pin, the fcb pin has a 0.18a internal current source pulling the pin high. include this current when choosing resistor values r5 and r6. the following table summarizes the possible states avail- able on the fcb pin: table 1 fcb pin condition 0v to 0.75v forced continuous both controllers (current reversal allowedburst inhibited) 0.85v < v fcb < 4.3v minimum peak current induces burst mode operationno current reversal allowed feedback resistors regulating a secondary winding >4.8v burst mode operation disabled constant frequency mode enabled no current reversal allowed no minimum peak current voltage positioning voltage positioning can be used to minimize peak-to-peak output voltage excursions under worst-case transient loading conditions. the open-loop dc gain of the control loop is reduced depending upon the maximum load step speci? cations. voltage positioning can easily be added to either or both controllers by loading the i th pin with a resistive divider having a thevenin equivalent voltage source equal to the midpoint operating voltage range of the error ampli? er, or 1.2v (see figure 8). the resistive load reduces the dc loop gain while main- taining the linear control range of the error ampli? er. the maximum output voltage deviation can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. a complete explanation is included in design solutions 10. (see www.linear.com) ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: %ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3728l-1 circuits: 1) ic v in current (including loading on the 3.3v internal regulator), 2) intv cc regula- tor current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current has two components: the ? rst is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents; the second is the current drawn from the 3.3v linear regulator output. v in current typically results in a small (<0.1%) loss. figure 8. active voltage positioning applied to the ltc3728l-1 i th r c r t1 intv cc c c 3728l1 f08 ltc3728l-1 r t2 downloaded from: http:///
ltc3728l-1 23 3728l1fc applications information 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit cur- rent. in continuous mode, i gatechg =f(q t +q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through the extv cc switch input from an output-derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(ef? ciency). for example, in a 20v to 5v ap- plication, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resis- tor, and input and output capacitor esr. in continuous mode the average output current ? ows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m, r l = 50m, r sense = 10m and r esr = 40m (sum of both input and output capacitance losses), then the total resistance is 130m. this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. ef? ciency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become signi? cant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = v in () 2 ? i max 2 r dr () ? c miller () f () 1 5v ? v t h + 1 v t h other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% ef? ciency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has ad- equate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. the ltc3728l-1 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky con- duction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to i load (esr), where esr is the ef- fective series resistance of c out . i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac ? ltered closed loop response test point. the dc step, rise time and settling downloaded from: http:///
ltc3728l-1 24 3728l1fc applications information at this test point truly re? ects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c ? lter sets the dominant pole-zero loop compensation. the values can be modi? ed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without break-ing the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the ? ltered and compensated control loop response. the gain of the loop will be in-creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during opera- tion. but before you connect, be advised: you are plug- ging into the supply from hell. the main power line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-battery. load-dump is the result of a loose battery cable. when the cable breaks connection, the ? eld collapse in the alterna- tor can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators ? nding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 9 is the most straightforward approach to protect a dc/dc converter from the ravages of an automotive power line. the series diode prevents current from ? owing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the ltc3728l-1 has a maximum input voltage of 30v, most applications will also be limited to 30v by the mosfet bvd ss . figure 9. automotive application protection v in 3728l1 f09 ltc3728l-1 transient voltage suppressor general instrument 1.5ka24a 50a i pk rating 12v downloaded from: http:///
ltc3728l-1 25 3728l1fc applications information design exampleas a design example for one channel, assume v in = 12v(nominal), v in = 22v(max), v out = 1.8v, i max = 5a, and f = 300khz. the inductance value is chosen ? rst based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the pllfltr pin to a resistive divider from the intv cc pin, generating 0.7v for 300khz operation. the minimum inductance for 30% ripple current is: l v in ?v out (f)(i ripple ) ? v out v i n or 3.7h. using standard inductor values: i l = v out (f)(l ) 1? v out v i n a 4.7h inductor will produce 23% ripple current and a 3.3h will result in 33%. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.84a, for the 3.3h value. increasing the ripple current will also help ensure that the minimum on-time of 100ns is not violated. the minimum on-time occurs at maximum v in : t on(min) = v out v in(max) f = 1.8v 22v(300khz ) = 273ns the r sense resistor value can be calculated by using the maximum current sense voltage speci? cation with some accommodation for tolerances: r sense 60mv 5.84 a 0.01 since the output voltage is below 2.4v the output resistive divider will need to be sized to not only set the output voltage but also to absorb the sense pins speci? ed input current. r1 (max) = 24k 0.8v 2.4v ? v ou t = 24k 0.8v 2.4v ? 1.8 v = 32k choosing 1% resistors: r1 = 25.5k and r2 = 32.4k yields an output voltage of 1.816v. the power dissipation on the top side mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p main = 1.8v 22 v 5 () 2 1 + (0.005)(50 c?25 c) [] ? 0.035 () + 22v () 2 5a 2
4 () 215pf () ? 1 5? 2.3 + 1 2.3 300khz () = 332mw a short-circuit to ground will result in a folded back current of: i sc = 25mv 0.01 ? 1 2 120ns(22v) 3.3 h = 2.1a with a typical value of r ds(on) and = (0.005/c)(20) = 0.1. the resulting power dissipated in the bottom mosfet is: p sync = 22v ? 1.8v 22 v 2.1a () 2 1.125 () 0.022 () = 100mw which is less than under full-load conditions.c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the downloaded from: http:///
ltc3728l-1 26 3728l1fc applications information maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (i l ) = 0.02(1.67a) = 33mv pCp pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 10. the figure 11 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continu- ous mode. check the following in your layout: 1. are the top n-channel mosfets m1 and m3 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the ltc3728l-1 v osense pins resistive dividers con- nect to the (+) terminals of c out ? the resistive divider must figure 10. ltc3728l-1 recommended printed circuit layout diagram c b2 c b1 r pu pgood v pull-up (<7v) c intvcc + c in d1 1f ceramic m1 m2 m3 m4 d2 + c vin v in r in intv cc 3.3v r4 r3 r2 r1 run/ss1sense1 + sense1 C v osense1 pllfltrpllin fcb i th1 sgnd3.3v out i th2 v osense2 sense2 C sense2 + pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 ltc3728l-1 l1 l2 c out1 v out1 gndv out2 3728l1 f10 + c out2 + r sense r sense f in 1f ceramic downloaded from: http:///
ltc3728l-1 27 3728l1fc applications information be connected between the (+) terminal of c out and signal ground. the r2 and r4 connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the ? lter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin con- nections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the opposites channels voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3728l-1 and occupy minimum pc trace area. figure 11. branch current waveforms r l1 d1 l1 sw1 r sense1 v out1 c out1 + v in ceramic c in r in + r l2 d2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3728l1 f11 r sense2 v out2 c out2 + ceramic downloaded from: http:///
ltc3728l-1 28 3728l1fc applications information 7. use a modi? ed star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging start with one controller on at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypically 10% to 20% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug- gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regula- tor bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly dif? cult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation.investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage. downloaded from: http:///
ltc3728l-1 29 3728l1fc typical applications figure 12. ltc3728l-1 high ef? ciency low noise 5v/3a, 3.3v/5a, 12v/120ma regulator 0.1f 0.1f 4.7f + 22f 50v d1 mbrs1100t3 d2 q1 q2 q3 q4 1f 10v cmdsh-3tr cmdsh-3tr 0.1f 10 0.01 0.015 3.3v 0.1f 20k 1% 105k, 1% 33pf 15k 33pf 15k 1000pf 1000pf 1000pf 1000pf 0.1f 20k 1% 63.4k 1% run/ss1sense1 + sense1 C v osense1 pllfltrpllin fcb i th1 sgnd3.3v out i th2 v osense2 sense2 C sense2 + pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 ltc3728l-1 t1, 1:1.8 10h l1 6.3h 150f, 6.3v panasonic sp 1f25v 180f, 4v panasonic sp gnd on/off 8 5 1 23 v out2 3.3v5a; 6a peak v out3 12v120ma 33f 25v v out1 5v3a; 4a peak v in 7v to28v 3728l1 f12 + + v in : 7v to 28v v out : 5v, 3a/3.3v, 6a/12v, 150ma switching frequency = 250khzmi, m2: fds6982s or vishay si4810dy l1: sumida cep123-6r3mc t1: 10h 1:1.8 dale lpe6562-a262 gapped e-core or bh electronics #501-0657 gapped toroid lt1121 + + 220k 100k 1m pgood 100k v pull-up (<7v) 59k 180pf 180pf m1m2 downloaded from: http:///
ltc3728l-1 30 3728l1fc typical applications figure 13. ltc3728l-1 5v/4a, 3.3v/5a regulator with external frequency synchronization 0.1f 4.7f, 10v + 22f 50v m1 pin 4 pin 4 q1 q2 q3 q4 m2 1f 0.1f 10 0.008 0.008 1f 50v f sync 3.3v 0.1f 10k 105k 1% 100pf 8.06k 100pf 4.75k 1000pf 1500pf 0.01f 1000pf 1000pf 1000pf 0.1f 20k 1% 63.4k 1% 20k 1% run/ss1sense1 + sense1 C v osense1 pllfltrpllin fcb i th1 sgnd3.3v out i th2 v osense2 sense2 C sense2 + pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 ltc3728l-1 l1 4.3h l2 4.3h 150f, 6.3v 180f, 4v gndv out2 3.3v/5a v out1 5v/4av in 7v to28v 3728l1 f13 + + v in : 7v to 28v v out : 5v, 4a/3.3v, 5a switching frequency = 250khz to 550khzm1, m2: fds6982s or vishay si4810dy l1, l2: sumida cdep105-4r3mc-88output capacitors: panasonic sp series 180pf 180pf 0.1f cmdsh-3tr cmdsh-3tr pgood v pull-up (<7v) 1f 50v downloaded from: http:///
ltc3728l-1 31 3728l1fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description .386 ? .393* (9.804 ? 9.982) gn28 (ssop) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 202122232425262728 19 18 17 13 14 16 15 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note:1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 5.00 0.10 (4 sides) note:1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 31 12 32 bottom viewexposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 packageoutline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typor 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) downloaded from: http:///
ltc3728l-1 32 3728l1fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 0708 rev c printed in usa related parts typical application figure 14. multioutput polyphase application phasmdclkout tg1tg2 0 i 1 i 3 i 2 i 4 90 open 180 u1 ltc3729 buck: 2.5v/15a buck: 2.5v/15a pllin tg1tg2 90 90 270 u2 ltc3728l-1 buck: 1.5v/15a 2.5v o /30a c in i in 12v in *input ripple current cancellation increases the ripple frequency and reduces the rms input ripple current thus, saving input capacitors i in * 1.5v o /15a 1.8v o /15a 3728l1 f14 buck: 1.8v/15a i 1 i 2 i 3 i 4 part number description comments ltc1628/ltc1628-pg/ ltc1628-sync 2-phase, dual output synchronous step-down dc/dc controller reduces c in and c out , power good output signal, synchronizable, 3.5v v in 36v, i out up to 20a, 0.8v v out 5v ltc1629/ ltc1629-pg 20a to 200a polyphase? synchronous controllers expandable from 2-phase to 12-phase, uses all surface mount components, no heat sink, v in up to 36v ltc1708-pg 2-phase, dual synchronous controller with mobile vid 3.5v v in 36v, vid sets v out1 , pgood lt1709/ lt1709-8 high ef? ciency, 2-phase synchronous step-down switching regulators with 5-bit vid 1.3v v out 3.5v, current mode ensures accurate current sharing, 3.5v v in 36v ltc1735 high ef? ciency synchronous step-down switching regulator output fault protection, 16-pin ssop ltc1736 high ef? ciency synchronous controller with 5-bit mobile vid control output fault protection, 24-pin ssop, 3.5v v in 36v ltc1778/ltc1778-1 no r sense current mode synchronous step-down controllers up to 97% ef? ciency, 4v v in 36v, 0.8v v out (0.9)(v in ), i out up to 20a ltc1929/ ltc1929-pg 2-phase synchronous controllers up to 42a, uses all surface mount components, no heat sinks, 3.5v v in 36v ltc3708 dual, 2-phase, dc/dc controller with output tracking current mode, no r sense , up/down tracking, synchronizable ltc3711 no r sense current mode synchronous step-down controller with digital 5-bit interface up to 97% ef? ciency, ideal for pentium ? iii processors, 0.925v v out 2v, 4v v in 36v, i out up to 20a ltc3728 dual, 550khz, 2-phase synchronous step-down controller dual 180 phased controllers, v in 3.5v to 35v, 99% duty cycle, 5x5qfn, ssop-28 ltc3729 20a to 200a, 550khz polyphase synchronous controller expandable from 2-phase to 12-phase, uses all surface mount components, v in up to 36v ltc3731 3- to 12-phase step-down synchronous controller 60a to 240a output current, 0.6v v out 6v, 4.5v v in 32v ltc3802 no r sense 2-phase dual synchronous step-down controller 330khz to 750khz, no sense resistor, output voltage tracking, synchronizable for 4-phase operation no r sense and polyphase are trademarks of linear technology corporation. downloaded from: http:///

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